module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output reg Z ); 

    reg[7:0] shift_reg;
    always@(posedge clk)begin
        if(enable)begin
            shift_reg	<=	{S,shift_reg[7:1]};
        end
    end
    
    wire[2:0] output_index = {A,B,C};
    always@(*) begin
        case(output_index)
            3'd0:Z=shift_reg[7];
            3'd1:Z=shift_reg[6];
            3'd2:Z=shift_reg[5];
            3'd3:Z=shift_reg[4];
            3'd4:Z=shift_reg[3];
            3'd5:Z=shift_reg[2];
            3'd6:Z=shift_reg[1];
            3'd7:Z=shift_reg[0];
            endcase
    end

    /*
    reg [7:0] q;
	
	// The final circuit is a shift register attached to a 8-to-1 mux.

	// Create a 8-to-1 mux that chooses one of the bits of q based on the three-bit number {A,B,C}:
	// There are many other ways you could write a 8-to-1 mux
	// (e.g., combinational always block -> case statement with 8 cases).
	assign Z = q[ {A, B, C} ];

	// Edge-triggered always block: This is a standard shift register (named q) with enable.
	// When enabled, shift to the left by 1 (discarding q[7] and and shifting in S).
	always @(posedge clk) begin
		if (enable)
			q <= {q[6:0], S};	
	end
    */

endmodule